1. Field of the Invention
The present invention relates to a device for controlling a non-volatile memory in which data can be electrically written and erased, more particularly to a technology for reducing an amount of time which is apparently necessary for writing data from a memory controller in the non-volatile memory.
2. Description of the Related Art
A conventional non-volatile memory control device, which is recited in the Japanese Patent Publication (No. 2004-253093 of the Japanese Patent Applications Laid-Open) is described referring to FIGS. 9-11C. FIG. 9 is a block diagram illustrating a constitution of a conventional EEPROM (Electrically Erasable Programmable Read Only Memory), FIG. 10A is a sectional view of a floating-gate memory cell transistor of the conventional EEPROM, FIG. 10B is an illustration of a constitution of a memory cell array, FIG. 11A is an illustration of a writing-time dependency of a writing-status threshold voltage of the conventional EEPROM, and FIG. 11B is an illustration of a threshold voltage distribution, and FIG. 11C is an illustration of a word-line-voltage dependency of a memory-cell current.
As shown in FIG. 9, an EEPROM 50 comprises a memory cell array 51, a sense amplifier circuit 52, a write data latch circuit 53, an address decoder circuit 54, a high-voltage control circuit 55, and a control circuit 56. The control circuit 56 is provided with a writing operation selector circuit 56a and a writing time control circuit 56b. The EEPROM 55 further comprises an output data switch circuit 57 and an input data switch circuit 58, and an output of the output data switch circuit 57 is inputted to the input data switch circuit 58 via a write data transfer bus B6.
As shown in FIG. 10A, a source 62 and a drain 63 are formed in a substrate 61 in a memory cell transistor 60, and a floating gate 65 is formed on a tunnel oxide film 64. A control gate 67 is formed on the floating gate 65 via an ONO (Oxide-Nitride-Oxide) film 66. A word line 71 is connected to the control gate 67.
In the memory cell transistor 60, a high electrical field is applied to the tunnel oxide film 64 so that a tunnel current is generated, and electrons stored in the floating gate 65 are thereby withdrawn or injected. As a result, a threshold voltage of the memory cell is controlled, and the data can be accordingly written and erased.
As shown in FIG. 10B, in the memory cell array 51, the memory cell transistors 60 are provided in a matrix shape at points at which a plurality of word lines 71 and a plurality of bit lines 72 respectively intersect with each other. Sources of the memory cell transistors 60 are respectively connected to source lines 73.
Next, an operation of the EEPROM thus constituted is described. When a writing instruction is issued, a temporary writing operation, in which the data is written at a high speed, is performed, and an additional writing operation, in which the reliability of the data writing is assured, is then performed. When the temporary writing operation and the additional writing operation are thus combined, the reduction of the writing time and the assurance of the reliability can be both realized. Below is given a more detailed description.
First, a temporary writing operation is executed to the EEPROM 50. In the temporary writing operation, the writing operation selector circuit 56a in the control circuit 56 selects the temporary writing operation in accordance with an input signal SSO, which is the writing instruction supplied from the memory controller not shown, and the writing time control circuit 56b sets a predetermined writing time. The predetermined writing time is a minimal amount of time demanded so that an initial reading operation, which is necessary for the additional writing operation described later, can be normally executed. For example, a writing time tp for this purpose is 1 ms, as illustrated in FIGS. 11A-11C, and is such a short period of time that stays in a single-digit number in comparison to a normal writing time of a two-digit number which guarantees the reliability (for example, tp=10 ms).
The high voltage control circuit 55 receives a control signal SS1 for the writing operation from the control circuit 56 and generates a high-voltage which is necessary for the writing operation, and supplies the generated high voltage to the write data latch circuit 53 and the address decoder circuit 54. The data to be written supplied via data buses B0 and B1 is retained in the write data latch circuit 53 via the input data switch circuit 58 and a write data bus B2. The write data latch circuit 53 and the address decoder circuit 54 supply the high voltage which is necessary for the writing operation to an address in the memory cell array 51 at which the data is written. The high voltage is supplied during a period of time set by the writing time control circuit 56b, and the temporary writing operation is thereby executed. The temporary writing operation is executed at a high speed.
Next, the additional writing operation is described. The additional writing operation includes operations in three stages, which are a data discriminating operation, a data transfer operation and a writing operation. When the input signal SSO including a data discriminating instruction, a data transfer instruction and a writing instruction is inputted from the memory controller, the control circuit 56 outputs the control signal SS1 to respective circuits. In the data discriminating operation, the sense amplifier circuit 52 discriminates the data temporarily written in the memory cell array 51. In the data transfer operation, the output data switch circuit 57 and the input data switch circuit 58 jointly transfer the temporarily written data to the write data latch circuit 53. In the writing operation, the data retained in the write data latch circuit 53 is written in the memory cell array 51. The respective operations are described below.
First, the data discriminating operation is described below. Current values of the memory cell transistors in the memory cell array 51 vary depending on the temporarily written data. When the data is discriminated by the sense amplifier circuit 52, therefore, a difference between the current value of the memory cell transistor and a constant reference current generated by a reference current control circuit 52a is used. More specifically, a voltage of 2 volts is applied to the word line of the memory cell transistor selected by the address decoder circuit 54 via an address bus AA2, and a voltage of 1 volt is applied to a bit line B4. A drain current flow between the bit line 72 and the source line 73 of the memory cell transistor selected at the time is inputted to the sense amplifier circuit 52 via a bit line B4. The drain current then is decided based on a word line voltage, a bit line voltage, a threshold voltage, and the like, of the selected memory cell transistor. When the output data is discriminated by the sense amplifier circuit 52, the drain current is compared to the reference current (for example, μA). In the case where the drain current is larger than the reference current, comparison data is “1”. In the case where the drain current is smaller than the reference current, the comparison data is “0”.
The data transfer operation is described below. The data outputted from the sense amplifier circuit 52 in the data discriminating operation is inputted to and retained in the write data latch circuit 53 via a read data transfer bus B5, output data switch circuit 57, write data transfer bus B6, input data switch circuit 58, and write data bus B2. In order to read the temporarily written data and output the read data outside from the EEPROM 50, the following operations are executed:                the output of the control signal SS1 by the control circuit 56 in accordance with the input signal SSO for the reading instruction from the memory controller;        the data discrimination in a manner similar to the description earlier; and        the read of the output data of the sense amplifier circuit 52 and the output of the read data via the data transfer bus B5, output data switch circuit 57 and data bus B7.        
The writing operation is described below. The writing time control circuit 56b sets a writing time longer than that of the temporarily writing operation. The writing time is set to be long enough for the reliability in the normal operation to be guaranteed. The data retained in the write data latch circuit 53 is written in the memory cell array within the writing time.
As a result of the data discriminating operation, data transfer operation and writing operation thus described, the data temporarily written in the memory cell array 51 is additionally written therein again, which guarantees the reliability in the data writing.
When the additional writing operation is thus implemented after the temporarily writing operation, which is a high-speed writing operation, in order to improve the writing reliability, an amount of time necessary for the data writing operation can be reduced, and the reliability in the data writing operation can be assured at the same time.
When a large volume of data is written at a high speed in the conventional EEPROM from the memory-controller side, there arise a too large number of memory blocks in the memory cell array already subjected to the temporary writing operation, which makes it difficult to secure an execution timing of the additional writing operation. As a result, the execution of the additional writing operation fails in some of the memory blocks, and the data writing performance cannot be as solid as expected, which deteriorates the writing reliability.